The Hot Take: ASML's monopoly needs get challenged, but not sure if Quantum will just make them invalid. We'll have to wait and see I guess.
Intel has entered high-volume manufacturing using ASML's High NA extreme ultraviolet (EUV) lithography technology for a subset of its Intel Core Ultra Series 3 "Panther Lake" processors, becoming the first company to ship high-volume logic products manufactured with the technology. ASML announced the milestone in an official press release on Wednesday, July 15, confirming that Intel Foundry is running the qualified High NA layers on its Intel 18A process node in Oregon.Go deeper with TH Premium: Chipmaking(Image credit: tsmc)A deeper look at the chipmaking supply chainTSMC's $165 billion U.S. investments examinedChina reportedly reverse-engineers EUV toolChina bets on DUV, as EUV blockade reshapes chipmakingAccording to ASML, Intel is using High NA EUV to pattern selected Intel 18A layers, with products already shipping to customers at yields matched to those achieved on ASML's existing NXE EUV platform. These layers are dual-qualified, meaning the same layer can be exposed on either an existing 0.33 NA NXE scanner or a 0.55 NA EXE scanner, with the resulting wafers being interchangeable.High NA EUV has long been viewed as the successor to today's EUV lithography, promising to extend semiconductor scaling by enabling manufacturers to print smaller, denser circuit patterns that are becoming difficult to achieve with existing tools. Until now, the platform had been confined to R&D work. ASML’s announcement marks the first time High NA EUV has been used to produce and ship a high-volume commercial logic product. Panther Lake, built on the Intel 18A manufacturing process, is spearheading this transition. Rather than replacing the company's entire lithography flow, Intel is applying High NA EUV to specific layers while the remainder of the chip continues to be manufactured using conventional lithography. High NA EUV builds on the same 13.5-nanometer extreme ultraviolet light used by today's scanners but increases the optical system's numerical aperture (NA) — how much light a lens system can collect and focus onto a silicon wafer — from 0.33 to 0.55. The higher value resolves finer features in a single exposure, allowing chipmakers to print smaller patterns with greater precision and process control.This increased resolution is expected to reduce reliance on complex multi-patterning techniques for some of the industry's most demanding layers, thereby simplifying manufacturing and improving feature fidelity. In the long term, these capabilities are expected to support higher transistor densities and improved performance in future processors, particularly as AI workloads continue driving demand for increasingly advanced semiconductor technologies."With increased resolution and better process control, the introduction of High NA EUV marks a substantial development in semiconductor lithography," said ASML President and CEO Christophe Fouquet. "We are proud to play a role in enabling the smaller, denser patterning that will accelerate advancements in AI and other emerging technologies." Intel and ASML have been working towards this milestone for several years. In 2024, Intel completed installation of one of the industry's first commercial High NA EUV lithography systems, the TWINSCAN EXE:5000, at its Hillsboro, Oregon, research and development facility. The company later became the first to qualify ASML's second-generation TWINSCAN EXE:5200B, which increases wafer throughput and overlay accuracy while incorporating an improved EUV light source over its predecessor.While the announcement represents High NA EUV's commercial debut, it does not mean Panther Lake is manufactured entirely using the new lithography platform. Instead, Intel has qualified High NA for selected layers, an approach that mirrors how new lithography generations are typically introduced into advanced semiconductor production before broader adoption across future nodes.Intel Foundry Executive Vice President and General Manager Naga Chandrasekaran said that qualifying the High NA process option on selected Intel 18A product layers enables the company's existing tool fleet to deliver higher manufacturing output while providing flexibility for future process technologies.Panther Lake itself is not a future product. Intel launched Core Ultra Series 3 at CES on January 5, 2026, opened preorders the following day, and put systems on shelves globally from January 27. The Core Ultra X9 378H followed in April alongside the value-tier Core Series 3, code-named Wildcat Lake, and the handheld-focused Arc G3 parts arrived on May 28.The announcement’s statement that the product is shipping to customers refers to wafer flow from the fab into the supply chain, rather than to a product launch. ASML says the two companies will continue working on High NA readiness, with the flexibility to incorporate the technology into future nodes based on customer needs — most immediately, Intel 14A, which Intel has designed to use High NA on a set of its tightest-pitch layers.
Intel is reportedly making a significant change to the manufacturing strategy for its upcoming Nova Lake processor family by shifting the majority of compute tile production back to Intel Foundry.
The Hot Take: Makes sense, especially if China takes Taiwan....
According to the Wall Street Journal (paywalled), Apple agreed to use Intel's U.S. chipmaking plants after White House officials pressured Tim Cook during tariff-relief talks last summer. MacRumors reports: In August 2025, Apple CEO Tim Cook was in Washington to lobby the Trump administration to drop its proposed 100 percent tariff on semiconductor imports -- a levy that would have raised costs across Apple's product line. Apple reportedly secured an exemption after pledging to invest hundreds of billions of dollars in the U.S., although many of those investments were already planned. During the meetings, president Trump and commerce secretary Howard Lutnick are said to have urged Cook to use Intel's fabrication plants to make some of Apple's chips. The link between the tariff talks and the Apple-Intel deal had not been previously reported.
Almost a year later, Trump announced via his Truth Social platform that Apple would begin using Intel-made chips in some products. "We need to design and build our Chips right here in America," the president posted. The news sent Intel shares to record highs. According to a person familiar with the negotiations cited by the WSJ, Apple plans to have Intel make chips for both Mac laptops and iPhones. The report doesn't say which chips or in what volume, and Apple is expected to remain reliant on Taiwan Semiconductor Manufacturing Company, or TSMC, for the majority of its custom silicon.
Read more of this story at Slashdot.
The Hot Take: Was almost like they were purposefully crippling their processors under past management.
Intel Nova Lake CPUs will mark the return of AVX-512, a feature that has long been abandoned by the company for its client CPUs. AVX-512 Is Coming Back To Intel's Consumer CPUs, Starting With Nova Lake Intel has had a love-hate relationship with AVX-512 on its consumer CPUs. The AVX-512 instruction set was last seen on Intel's Tiger Lake (11th Gen) family, and since then, the company has offered no support for it on its modern-day chips. Meanwhile, AMD has been offering AVX-512 support on its Zen 4 and Zen 5 chips, both client and server platforms. Last year, we […]Read full article at https://wccftech.com/intel-nova-lake-cpus-to-bring-back-avx-512-support-six-years-after-it-was-abandoned/
Intel has published a new patent on its XBM memory, which is proposed as a replacement for HBM4, offering much higher bandwidth capabilities. XBM vs HBM: Intel's New Proposed DRAM Solution Extends To 32 GT/s Speeds, While Reducing Costs Through UCIe Links HBM continues to be the standard for AI accelerators, but more recently, we have seen LPDDR memory being used to overcome shortages, prices, and power associated with the standard. Intel's past attempts at DRAM, such as HMC (Hybrid Memory Cube) and MCDRAM, faced various issues and never came to market, but with XBM, Intel is course-correcting its DRAM […]Read full article at https://wccftech.com/intel-xbm-memory-takes-aim-at-hbm4-32-gt-s-speeds-lower-costs-through-ucie-links/
The Hot Take: I really wonder if this will deflate the Ai bubble even a little bit.
The x86 Ecosystem Advisory Group led by Intel and AMD recently firmed up the AI Compute Extensions (ACE) specification for optimizing x86 for AI computation tasks around matrix multiplication and the like for machine learning workloads. The cross-vendor ACE extension is ultimately a successor to Intel's Advanced Matrix Extensions (AMX). Posted to the GCC mailing list today by Intel engineers are the initial patches in preparing the compiler support for ACE...
The Hot Take: Intel Ramping things up to play catch up and win volume from TSMC.
Intel this week initiated expansion of its Bowers Campus in Santa Clara, California, in a bid to produce more photomasks (reticles) in the U.S. The company intends to build a new manufacturing facility and a new utility building at the site, which will reinforce the site's position as a key producer of photomasks for Intel.Go deeper with TH Premium: Chipmaking(Image credit: tsmc)A deeper look at the chipmaking supply chainTSMC's $165 billion U.S. investments examinedChina reportedly reverse-engineers EUV toolChina bets on DUV, as EUV blockade reshapes chipmakingEarlier this year Intel obtained approval to build a new 107,000 square feet (9,940 square meters) manufacturing facility with Class 1 cleanroom at its Bowers Campus, and this week it formally began construction on the expansion, which it kicked off at a ceremony attended by its top executives and Santa Clara mayor Lisa Gilmor. The new facility will be able to write 6-inch × 6-inch photomasks both for DUV and EUV layers and a variety of nodes (from 32nm down 1.4nm-class), though the primary focus of the facility is to produce reticles for leading-edge process technologies — such as Intel's 18A, 18A-P, 14A, and more advanced — that rely on advanced DUV, EUV and eventually High-NA EUV tools and require more advanced photomasks, such as those that feature extremely dense patterns and use curvilinear optical proximity correction (OPC) with curved geometric shape.(Image credit: Intel)Intel is one of a few leading chipmakers in the world that still maintains a world-class mask writing shop — which is important, as every advanced product requires hundreds of masks, and every mask revision directly affects production schedules. In addition, producing masks in-house is getting particularly important when it comes to reticles for EUV layers as EUV tools tend to damage masks over time (despite usage of protective pellicles), so having the ability to make new masks in a short amount of time is crucial. Furthermore, Intel is the only semiconductor producer to make its own tools for photomasks writing at its IMS Nanofabrication subsidiary. Historically, reticles were patterned using a single e-beam tool, which was slow. By contrast, IMS produces multi-beam mask writers (MBMWs) that project 262,144 independently programmable electron beams simultaneously, which increases throughput by orders of magnitude at a nanometer-scale placement accuracy.(Image credit: Intel)"Santa Clara has been home to some of Intel's most important manufacturing innovations for decades," said Dr. Frank Abboud, VP Intel Foundry & GM of Intel Mask Operations. "By expanding the Bowers campus mask operations, we're strengthening a critical capability that supports advanced process technology production around the world and reinforces Intel Foundry's commitment to advancing U.S. semiconductor manufacturing leadership."Intel's Bowers Campus in Santa Clara has been dedicated to mask production since 1986. The site forms the company's primary mask manufacturing infrastructure supporting together with the company's facility in Hillsboro, Oregon. Production of non-critical masks has historically been outsourced, though we do not know whether the company still does that.IntelIntel
The Hot Take: Oh so the Ultra series aren't just crap then? /smh
It's curious to call this one a leak, exactly, since the original source is direct from AMD and live on the web, but here we go: AMD's Vishal Badole submitted a patch for the Linux Kernel that he describes as adding support for "a Low Power core type, in addition to the existing Performance and Efficiency types." That's pretty clear-cut.
Now,
The Hot Take: Interesting, Risc-V shop from rockstar architect Jim Keller.
Jim Keller isn't bothered by Cerebras's recent IPO and says that he welcomes it, but Tenstorrent will still beat them on everything. Tenstorrent CEO, Jim Keller, Signals Deal With Intel or Qualcomm While Promising To Beat Cerebras "on everything" Tenstorrent recently introduced its latest BlackHole Galaxy server, a system with which it can disrupt the entire AI segment, with performance levels that crush the competition. We covered the announcement last month when the company demoed its Blackhole server undercutting a NVIDIA GB300 with up to five times better TCO. Keller Accepts The Challenge To Beat NVIDIA, Cerebras & Others At […]Read full article at https://wccftech.com/jim-keller-cerebras-ipo-was-helpful-tenstorrent-to-beat-them-on-everything/
The Hot Take: I just hear Tim Allen in my head from tool time.
Intel is expected to push the boundaries on power draw with its upcoming Nova Lake series processors, which will rival the best CPUs. According to newly leaked information, the flagship 52-core desktop variant is expected to feature a dual-compute tile architecture with a massive PL2 limit of 474W. The information was shared by LC Tech Leaks and confirmed by Jaykihn, who has a pretty solid track record with Intel hardware.PL2, or Power Limit 2, represents the maximum power a CPU can draw during short boost periods. That said, a PL2 target of 474W remains quite demanding, although a previous rumor suggests Intel may also have a PL4 emergency power limit over 700W. It is important to note that these power limits may only apply to the top-end models with the dual-tile architecture.Additionally, the leak also sheds light on the upcoming platform, including the previously rumored LGA1954 socket. We already know that Nova Lake-S will require a new generation of motherboards. Motherboard vendors are expected to classify their boards by sustained PL1 power levels, with configurations for 35W, 65W, 125W, and 175W CPUs. Enthusiast-grade motherboards, likely the Z990 series, are also rumored to feature three EPS 8-pin CPU power connectors instead of the traditional two. While vendors will have the option to include a third connector, its primary purpose would be to support extreme overclocking and would not affect the CPU's rated performance profile.The upcoming Nova Lake-S lineup is expected to carry the ‘Core Ultra 400S’ moniker and will be Intel's biggest desktop CPU overhaul in years. We’ve previously reported leaked specifications indicating configurations ranging from 6 to 52 cores, with support for DDR5-8000 memory. The flagship 52-core model is expected to feature 16 performance cores, 32 efficiency cores, and a new Big Last Level Cache (bLLC) design to take on AMD's 3D V-Cache gaming dominance. The company is also rumored to introduce integrated Xe3 graphics, Thunderbolt 5, PCIe 5.0 connectivity, and an upgraded NPU for AI workloads.While these specifications are unconfirmed, it is clear that Intel is targeting substantial gains in gaming, multi-threaded performance, and overall platform capabilities with its next-gen processors.