The Hot Take: That sounds alot like an ASIC...
In AMDâs latest bid to upset Nvidia's dominance in AI hardware, the House of Zen has acquired AI chip company Taalas, which bakes model weights directly into silicon in a process that promises to boost inference performance by an order of magnitude or more. The deal, announced at market close on Thursday, appears to be framed in much the same context as Nvidiaâs $20 billion licensing deal with Groq last December: make high-performance âpremiumâ inference services prized for AI agents, like code assistants, faster and cheaper to run. AMD didnât disclose the terms of the deal, but from what we understand, this is an actual acquisition rather than an acquihire. Founded in 2023 and based in Toronto, Taalasâ approach to inference is radically different from conventional GPUs or the dataflow architectures that underpin Groq LPUs or Cerebras' waferscale accelerators. A model-specific integrated circuit The startupâs chips donât rely on HBM to store the model weights but rather etch them directly into the silicon. In a sense, Taalasâ chips are really model-specific integrated circuits or MSICs. Perhaps more importantly, Taalasâ tech isnât just conceptual. In February, the startup revealed its first test chip fabbed on TSMCâs 6nm process tech, which it called the HC1. Initial benchmarks saw the chip serve Metaâs Llama 3.1 8B at a blistering 16,960 tokens a second â when announced last February, that was 48x faster than Nvidia's GPUs and 8.5x faster than Cerebras' accelerators. While Llama 3.1 is ancient by todayâs standards, having made its debut all the way back in mid 2024, the reticle-sized chip was really intended to prove the concept. Taalas has been incredibly secretive about how its chips actually work, but we know its processors are comprised of two main regions: the mask-ROM recall fabric where model weights are etched, and the SRAM recall fabric where KV caches and fine-tuning adapters are stored. For its second-gen HC2 chip due out this summer, Taalas aims to boost parameter count to 20 billion parameters. That might not sound like much, but just like with GPUs for larger models, weights are simply distributed across multiple accelerators using pipeline parallelism. At 20 billion parameters per chip, youâd need just 50 accelerators to support a trillion-parameter model, and AMD just so happens to have a rack-scale compute platform and in-house system design team that can comfortably accommodate that. Thatâs quite a bit more space and power efficient than Nvidiaâs recently unveiled LPX systems, which would need a few dozen GPUs and at least 2,000 Groq LPUs to serve the same model. From what we understand, AMD intends to pair its Instinct-based Helios racks with chips based on Taalasâ tech, which implies a disaggregated architecture where compute-heavy prompt processing is done on GPUs while token generation is offloaded to Taalas-based accelerators. Itâs also possible that AMD could adopt a sort of tick-tock cadence in which customers initially deploy and validate models on Instinct accelerators and, once theyâre satisfied with them, transition to Taalas accelerators. We can only speculate at this point, but hereâs what AMDâs SVP of AI, Vamsi Boppana, had to say about it in a canned statement: âAMD is building a full-stack AI platform that gives customers the flexibility to deploy the right compute solutions for every AI workload." You better really love that model While the tech is blazing fast, if you hadnât already figured it out, it comes with a pretty substantial downside. Once the chips are deployed youâre stuck with that model. Any change bigger than something like a LoRA adapter is going to require a re-spin of the chips, which is not only expensive but time-consuming. Nearly four years into the AI boom, new models are rolling out on a nearly monthly basis. In order to benefit from Taalasâ tech, AMDâs customers are going to have to be really sure about their choice of models, which will be easier for some than others. However, if the startup is to be believed, the situation isnât quite as bad as it sounds. While new models will require a re-spin, it doesnât require starting over from scratch. Instead, just two layers of metal need to be changed, which is a lot cheaper and less time-consuming. With that said, we strongly suspect this tech will largely be deployed by AI model devs, their infrastructure providers, and a handful of inference providers. In an interview with our sibling site The Next Platform in February, the company suggested that etching a model's weights into silicon is 100x less expensive than training a frontier model. AMD is certainly in a position to negotiate those deals. OpenAI, Anthropic, and Meta are all major Instinct customers. Given the close working relationship between the model houses and the chip designer, it wouldn't be surprising to see a GPT or Claude deployed on a combination of Taalas and instinct accelerators. The tech also has implications for model development. One of the ways developers have cut down on hallucinations is by trading time for accuracy. The technique, called test-time scaling, is quite simple in practice, and involves allowing a model to âthinkâ for longer before responding. One drawback of test-time scaling is that it consumes substantially more tokens, which makes it expensive, and means users have to wait longer for the chatbot, code assistant, or agent to respond. If AMDâs Taalas buy can drive down the cost per token and boost output speeds by 10x or 20x, model devs may opt to extend the reasoning time even further. In any case, we may not have to wait long to see just how Taalas fits into AMDâs broader vision. Subject to regulatory approval, the deal is expected to close in the fourth quarter. ÂŽ
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The Hot Take: So when is there going to be a price fixing class action for GPUs?
AMD is reportedly preparing to jack up graphics card prices after waiting for Nvidia to blink first.
According to PC Gamer the word comes from industry watcher Harukaze5719 who reckons AMD was holding fire until Nvidia pushed up its own prices.
âThis was to avoid the risk of declining product competitiveness and market share loss from a hasty price adjustment during a period of demand pressure,â Harukaze5719 wrote on X.
AMD has already warned manufacturers about a price rise of âat least 10 per centâ across all products. The increase is said to kick in from the start of August, which is handy timing if you enjoy paying more for the same silicon.
âThe price positioning is expected to be similar to that of the Nvidia series graphics cards,â Harukaze5719 wrote.
Last week, Nvidia was said to be preparing graphics card and component price rises of 20 to 30 per cent. Samsung was tipped for similar rises on memory units, because apparently the hardware industry looked at gamers and decided they had too much rent money left.
The main culprit is the AI data centre feeding frenzy. Those outfits are hoovering up components and cutting fat deals to grab stock before consumer buyers get a sniff. Harukaze5719âs analysis pointed to a current âweak recovery phase in the consumer graphics card marketâ.
It cited âhigh price sensitivity at the end-user levelâ and âexisting inventory still needing to be digestedâ as reasons AMD had been cautious. The mess is spilling into consoles too. For decades, console prices usually fell after launch as production matured and platform holders chased a wider audience. Now Nintendo, Sony and Microsoft have all raised console prices since release, sometimes more than once.
They have warned that more increases could follow, which is lovely news for anyone still pretending gaming hardware is a cheap hobby. The knock-on effect could push next-generation consoles close to ÂŁ1,000, about âŹ1,170, for the first time.
A thousand-quid console used to sound like satire. Now it looks like a PowerPoint target somewhere in procurement.
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The Hot Take: Well there goes CPU stocks.
Intel and AMD are signing long term agreements with Chinese data center firms to provide them with CPUs for AI computing, says a report from Reuters. CPUs in AI computing rose to prominence earlier this year after agentic AI demand reshaped the market. Agentic computing places a greater emphasis on CPUs, and according to the sources, the deals are motivated by the rapid price rise due to high demand. AMD & Intel Set To Cover A Year's Worth Of CPU Supplies To Chinese AI Data Centers, Says Report The surge in AI demand for CPUs has also led to Intel [âŚ]Read full article at https://wccftech.com/intel-and-amd-lock-in-year-long-cpu-deals-with-chinese-ai-firms-as-prices-surge-40/
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The Hot Take: Will have to take this with a bit rock of salt until we see the benches and real world performance. Just a price grab or actual performance?
AMD is apparently no longer satisfied with being perceived as a perennial underdog, and is reportedly choosing to make a bold statement by pricing its Helios rackscale solution at a hefty premium to NVIDIA's Rubin. What's more, AMD has reportedly managed to rope in Microsoft as the product's first confirmed client, demonstrating the utility that Helios offers even at its supposedly elevated price point. Futurum believes AMD will price Helios at $5 million to $5.5 million per rack, versus an expected retail price of $3.5 million to $4 million for the second-gen NVIDIA Rubin rack As we explained in a [âŚ]Read full article at https://wccftech.com/amd-is-reportedly-pricing-its-helios-rack-40-above-nvidias-second-gen-rubin-confident-that-customers-will-pay-the-premium/
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The Hot Take: Oh so the Ultra series aren't just crap then? /smh
It's curious to call this one a leak, exactly, since the original source is direct from AMD and live on the web, but here we go: AMD's Vishal Badole submitted a patch for the Linux Kernel that he describes as adding support for "a Low Power core type, in addition to the existing Performance and Efficiency types." That's pretty clear-cut.
Now,
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The Hot Take: We'll see how long before they go to Intel because TSMC is filled up in Arizona FABs.
Nvidia will stay TSMCâs biggest customer in 2027, but AMDâs EPYC Venice could pinch the CPU bragging rights.
TSMC is seeing rising demand for 2.5D advanced packaging as CPUs become more important in the agentic AI bunfight. Apparently, GPUs alone are no longer enough to feed the machine.
Morgan Stanley reckons Nvidia will remain TSMCâs largest CoWoS customer in 2027. TSMC is expected to reach wafer capacity of 200,000 wafers a month that year.
Nvidia is using TSMCâs CoWoS packaging for two main product families. CoWoS-L is for AI GPUs such as Blackwell and Rubin, while CoWoS-R is for Vera CPUs.
CoWoS-L capacity is expected to hit about 910,000 units, up 40 per cent year on year. Vera shipments are expected to double, which would help Nvidia lift data centre revenue by 52 per cent.
Morgan Stanley said:âNvidia uses TSMCâs CoWoS-L as the single source for all its AI GPU products (e.g. Blackwell and Rubin). Its 2027 CoWoS-L consumption could reach ~910k, up ~40 per cent year on year. Strong CoWoS-R bookings by Nvidia suggest room for AI GPM products (such as doubling). Taken together, we estimate Nvidiaâs 2027 forecast for Nvidiaâs data centre revenue to rise 52 per cent year on year.â
Nvidia has been pivoting harder into CPUs to claw back China revenue after GPU restrictions. Several customers have shown interest in Vera CPUs.
The company has hand-delivered the first Vera CPUs to Anthropic, OpenAI, SpaceX and Oracle. Nothing says âagentic AI eraâ like an expensive chip being passed around the usual suspects.
The problem for Nvidia is that AMD is not politely standing at the back. Its next-generation EPYC Venice platform is already in volume production at TSMC.
Venice is based on AMDâs upcoming Zen 6 architecture and is expected to deliver better performance and efficiency. It targets both AI and HPC, while Vera is being pitched squarely at agentic AI.
Morgan Stanley projects Nvidiaâs Vera CPUs could reach 5.75 million units by 2027. AMDâs EPYC Venice, though, could reach 6.75 million units in 2027. That is 17 per cent more than Vera and 5.4 times its expected 2026 volume.
âBased on our CoWoS consumption forecasts, Nvidiaâs 5nm Vera CPU could grow to 5.75mn units in 2027, while AMDâs 2nm Venice CPU may reach 6.75mn units in 2027 vs. ~1.25mn in 2026,â the beancounters said.
AMD has another advantage on paper, with Venice using TSMCâs advanced 2-nanometre process. Vera is based on a 3-nanometre process. The real headache for both companies may not be each other. It is custom silicon, where the cloud crowd is deciding that buying chips off the shelf is for the riffraff.
OpenAI, Google, Amazon and others are either talking up custom chips or already building them. That turns the AI supply chain into a fight between outside suppliers and in-house silicon vanity projects.
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The Hot Take: Why did it disappear in the first place?
AMD has confirmed that it will restore Transparent Secure Memory Encryption (TSME) support on consumer Ryzen processors after previously removing the feature through AGESA firmware updates.
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The Hot Take: AMD getting ready for Intel refocus on HPDT?
With Threadripper, it has always been a bit like heavy-haul transport on the motorway: massively overdimensioned for normal users, but for certain workloads exactly the kind of tool where every additional lane matters. Now AMDâs next workstation generation has become tangible for the first time. An entry for âTR6 Mustang Peakâ has appeared in AMDâs [âŚ]
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The Hot Take: Making the CPU important again on the x86 platform.
ACE, the upcoming set of x86 Extensions defined by both AMD & Intel, has seen the latest spec release, focusing on AI acceleration. AMD & Intel Focus on AI Acceleration Through Next-Gen x86 Architectures That Are ACE Compliant Last year, Intel and AMD partnered to strengthen the x86 ecosystem through their "x86 Ecosystem Advisory Group" initiative. The plan was to offer a standardized set of features across architectures to make x86 accessible, scalable, and compatible with future requirements. Four key features were announced: FRED, AVX10, ChkTag, and ACE. Now, the latest ACE "AI Compute Extensions" specifications have been published by AMD [âŚ]Read full article at https://wccftech.com/amd-intel-arm-x86-with-ace-matrix-multiply-engines-low-precision-ai-formats-future-cpus/
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The Hot Take: Well now....
AMD appears to have yanked a memory encryption protection from consumer Ryzen chips, leaving users to play firmware detective.
For those who came in late: a decade ago, AMD added Transparent Secure Memory Encryption (TSME) to higher-end CPUs to protect systems from cold-boot attacks and other physical exploits that can siphon data from memory. The feature encrypts everything stored in RAM, making stolen memory contents useless to attackers with physical access.
Over time, TSME turned up on cheaper Ryzen consumer chips, and privacy-minded users reasonably started treating it as part of the package.
Recently, without warning, that protection vanished from lower-end AMD chips in a way Windows users could not easily detect and Linux users could spot only with some technical faffing.
According to Ars Technica AMD has not explained why TSME worked on these CPUs or fully confirmed the change, saying only that TSME âis a security feature only applied to PRO CPUs as part of AMD PRO Technologies.â
In April, Linux hobbyist Ben Kilpatrick installed a new operating system on a Ryzen 7 9700X system and ran Host Security ID to check firmware and hardware protections. He found HSI reporting âencrypted RAM: not supportedâ, even though TSME had been enabled in BIOS and had previously shown as âencryptedâ.
Kilpatrickâs digging led MSI engineers to test consumer Ryzen chips on MSI and Gigabyte boards, where older AGESA firmware enabled TSME but newer AGESA 1.2.7.0 showed it as unsupported.
Pro Ryzen chips supported TSME across motherboard brands and firmware versions, which rather spoiled the idea that this was just a random board-level wobble.
âThe big outstanding question is whether this is a deliberate policy decision by AMD to restrict TSME to PRO chips, or an unintentional regression that was introduced in AGESA 1.2.7.0,â Kilpatrick told Ars.
After Kilpatrick filed a bug report on AMDâs public engineering GitHub, AMD fellow software engineer Tom Lendacky suggested toggling the BIOS option and then speaking to MSI if that failed.
AMD senior principal software engineer Mario Limonciello gave similar advice, telling him: âIf it still doesnât work; then yes please report it to your board vendor to debug.â
Kilpatrick later said MSI had been told by AMD that TSME was officially supported only on PRO processors, and tests showed TSME active on a Ryzen 9945 PRO but off on a consumer Ryzen 9800X3D.
MSIâs ABL dump comparisons reportedly showed the internal AGESA flag DfIsTsmeEnabled returning FALSE for consumer chips, even when TSME was set to AUTO or ENABLED in BIOS.
Kilpatrick pressed AMD on whether this was a silicon limitation or a firmware policy decision, because one is fixed and the other could be changed.
Limonciello replied: âMy apologies, but I donât have any more information to share on this topic.â
This is embarrassing as Lendacky said in 2020 that a consumer Ryzen 3700X âshould support TSMEâ, and in 2025 recommended using it if the BIOS exposed the option.
Silicon-level security expert Joe Fitzgerald said: âBut I really feel like an explanation should be in order, even if it was âTSME was never supposed to be supported. We did ship some firmwares that erroneously enabled it, but you shouldnât use them since we canât guarantee itâll work properly.ââ
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